The development of wireless mobile communications and Radio Frequency (RF) standards have entailed the need of linear Power Amplifiers (PA) while reducing the power consumption on the battery.
Some techniques are already known for improving the efficiency of RF power amplifiers, based on the use of complex circuits, sophisticated linearization circuits and feedback loop.
Another simple structure which is known is based on the class AB power amplifier having an input 6 and an output 7, such as illustrated in FIG. 1, which comprises a MOS transistor 1 having a gate receiving, through a capacitor 4 an input signal Vin (RFinput) and a drain connected to a Vdd voltage via an inductor 2 and also connected to the RF out output terminal 7 (driving a load ZL 5) via an output capacitor 3.
FIGS. 2a and 2b are flow charts respectively illustrating both the current consumption Icons (as a function of the output power PPout) and the gain Gm of such amplifier depending on the size of the transistor. It can be seen that the current consumption follows a curve that is function of the input RF swing as presented in FIG. 1. For a targeted output power Pout, a load ZL is determined and Icons is then mainly driven by Pout. The quiescent current Iq has been represented in FIG. 2a and corresponds to the point of no or little RF input signal. This particular point is determined by an appropriate biasing circuit (not illustrated in FIG. 2) which is DC set regarding bias point at G and transistors size.
When one considers the situation of high levels of the input signal or, in other words when the output power becomes higher, one determines the particular size of the transistor accordingly, by considering current capabilities (electromigration for instance).
The Power Gain (PG) is mainly given by the ratio between the output voltage and the input voltage. Typically PG is around 8-10 dB. Moreover, because of a possible “oversizing”, the typical gain (or gm) for a MOS transistor is not linear anymore with the size, as illustrated in FIG. 2b, especially once the cell is sized for current.
The drawback resulting from a high size of the transistor comes from the fact that the latter then shows an efficiency (Power Amplifier Efficiency PAE) which is no longer optimized because of higher quiescent current Iq. Linearity is also an issue because of too much capacitance at the transistor ports.
Clearly, the power amplifier is sized at high power but not at low power which represents 80% of the time.
There is therefore a dilemma to be considered with the simple amplification structure of FIG. 1.
Either the designer focuses on the power consumption and the transistor is then (under)sized so as to only draw minimal quiescent current Iq.
Or conversely, the designers may decide to (over)size the transistor so as to generate a high amount of power Pout, thus increasing the value of the quiescent current Iq.
There is therefore a desire for a new circuit which aims at reducing the power consumption and particularly Iq and also shows a high linearity even at high level of output power Pout.
Such is the aim of the present invention.